Bharat Book Bureau

WLP & Embedded Die Technologies 2008

If we take a look at the amazing learning curve of the semiconductor industry in terms of chip density versus cost improvements over time, it is easy to realize that a gap is widening between the scaling evolutions of the chip front-end and the packaging-assembly manufacturing industries.

Wafer level packaging (WLP) is all about filling that gap: by making the packaging and assembly steps a whole collective wafer level process, packaging has now the potential to scale with the cost and size evolutions of most stringent semiconductor applications. As a generic description, WLP should be defined as “all packaging and assembly process steps are done at the wafer level, the last step being the chip dicing”. As a consequence of this, WLP does not require any intermediate substrate interposer: wafer level packaged components are directly “surface mountable” onto the circuit board. WLP is definitively a breakthrough packaging technology to be widespread even into the most cost sensitive applications as it will scale favorably with the trend to manufacture on ever increasing wafer diameters.

Actually, it is difficult to estimate what is the real status of volume production for WLP. This new packaging report aims at giving clues for understanding the technologies, trends and market status of WLP in Semiconductor ICs, CMOS imagers and MEMS applications.

WLP & Embedded Die Technologies 2008 report ( http://www.bharatbook.com/Market-Research-Reports/WLP-And-Embedded-Die-Technologies.html )gives a precise description of the different type of devices using WLP and their related manufacturing challenges. Examples of major market findings are:

For CMOS imagers, WLP is indeed already an industrial reality. Today, about 35% of CMOS imagers to be found into latest consumer cell-phone and notebook cameras are encapsulated in a WL-CSP. We forecast that the technology could penetrate about 63% of this market as of 2012 as it will progressively widespread from CIF/VGAs to higher resolution image sensors.

Semiconductors integrated circuits indeed represent the largest potential for WLP. It used to be mostly restricted to small I/Os applications such as integrated passive devices, LED drivers and amplifiers. However, WLP technology tends now to integrate higher I/Os devices (>50) and manufactured on ever larger wafer diameters (6”, 8” and 12”). Thus, we forecast WLP technology to grow from 1% of the mainstream IC with about 6 billions of units up to 2.5% by 2012. GaAs wireless RF chips are one of the most dynamic market segments with an expected CAGR > 100% over the 2007-2012 time period. Our analysis coers power, SAW, FBAR, logic, analog and memory devices as well.

For MEMS, the term “WLP” has been extensively used in the industry since many years now. However, it is more a WLC “Wafer Level Capping” approach that is currently developed and not a real “true WLP”. Actually, production of first real WLP for MEMS started in 2006 and will account for a significant proportion of the WLP market by 2012 (see related figure 2). Companies like Samsung (KR), Dalsa Semiconductor (CA), Hymite (DK), Silex Microsystems (SW), Infineon (GE), IMT (US), TMT (TW) and VTI (FI) have all reported advanced developments in this area. Different types of MEMS going to WLP have been analyzed: inertial (gyroscopes, accelerometers), RF (switch & resonators), Si-microphones, Biochips and optical MEMS. Proportion of MEMS devices to be encapsulated in a real WLP is going to rapidly expand in volume with a CAGR above 100% over the 2007-1012 time periods.

Ultimately, WLP market value has been evaluated over 2007-2012 for MEMS, GaAs wireless, CMOS image sensors, power devices, SAW, FBAR, logic, memories and IPDs. Market forecasts have being established at the material, equipment and device levels, in both wspy (wafer start per year) and in MUS$

“WLP & Embedded Dies Technologies” report covers the manufacturing challenges faced for the wafer level packaging of MEMS, CMOS image sensors and Semiconductor ICs. Technology issues are presented and discussed in details such as encapsulation processes (wafer bonding, thin film), lithography (stepper vs. mask aligners), materials associated (dry films, liquid, negative and positive photoresists), deposition methods (Spin, Spray coating, EDPr plating on high topographies…), non-lithographic processes (such as ECPR), Bumping technologies (Ball loading, electroplating copper pillars, solder, gold microbumps, screen printing techniques, C4NP), passivation layers for the UBM, RDL and TSV process steps (based on polyimide, BCB, PBO, SU8…).

It also covers in a separate chapter a presentation of the different technologies and integration requirements for embedded dies at the substrate level. This is a relatively new 3D approach developed by the PWG industry in order to meet the integration requirement of next System in Package (SiP) module configurations.

For vast range of market reports please visit: http://www.bharatbook.com/Market-Research/Semiconductors.html

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Comments

  1. Wonderful article. I been looking for one on a similar note. I guess you always have something up your sleeve

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